Del 06-03-2025 al 07-03-2025
Seminario Gratuito – Embedded Heterogeneous Design in AMD Adaptive SoC
Embedded Heterogeneous Design in AMD Adaptive SoC (Free Hands-on Workshop / Taller práctico gratuito)
* This is a free of charge seminar sponsored by AMD (Regular Price 999 u$d). The seminar will be in Spanish.
Introduction (in Spanish Below):
In this workshop we would continue exploring the AMD adaptive SoC (mainly but not only Versal) and particularly going deep in the design Flow. This talk covers the AMD Versal™ architecture and illustrates the tool flow for developing HLS (High Level Synthesis) components as well as integrating an entire system project when designing an embedded heterogeneous system using the v++ tools and AMD Vitis™ Unified IDE.
The emphasis of this seminar is mainly on:
- Describing an embedded heterogeneous system design
- Illustrating the AMD Versal adaptive SoC architecture, NoC, and AI Engine
- Describing an AMD design tool flow (for Versal and others AMD SoC)
- Developing HLS and AIE components using the AMD Vitis tool
- Utilizing the v++ command line tools for component compilation, linking, and packaging to run emulation
- Demonstrating the system design flow for a heterogeneous embedded system using the AMD Vitis Unified IDE
Introducción (en castellano):
En este seminario/taller continuaremos explorando el SoC adaptativo AMD (principalmente Versal, pero no solo) y profundizaremos particularmente en el flujo de diseño. Esta charla cubre la arquitectura AMD Versal™ e ilustra el flujo de herramientas para desarrollar componentes HLS (High Level Synthesis), así como la integración de un proyecto de sistema completo al diseñar un sistema heterogéneo integrado utilizando las herramientas v++ y AMD Vitis™ Unified IDE.
Este seminario se centra los siguientes aspectos
- Describir el diseño de sistemas heterogéneos integrados (heterogeneous system design)
- Ilustrar la arquitectura SoC adaptativa AMD Versal, NoC y AI Engine
- Describir un flujo de herramientas de diseño AMD (para Versal, MPSoC, y Zynq)
- Desarrollar componentes HLS y AIE utilizando la herramienta AMD Vitis
- Utilizar las herramientas de línea de comandos v++ para compilar, enlazar (link) y empaquetar componentes para ejecutar la emulación
- Demostrar el flujo de diseño de sistemas para un sistema integrado heterogéneo utilizando el IDE unificado AMD Vitis
* Este taller es gratuito gracias a AMD. (Costo regular de 999 u$d)
Agenda (preliminary):
- Introduction to AMD Embedded Heterogeneous Design
- Adaptive SoC: Architecture Overview (emphasis on Versal devices)
- Application Mapping and Partitioning in Adaptive SoC
- Driving the AMD Vitis Unified IDE
- Tool Flow for Heterogeneous Systems
- Introduction to AMD Vitis High-Level Synthesis (HLS) Components
- Vitis HLS: Methodology and Optimization Techniques
- AI Engine Programming: Kernels and Graphs
- AI Engine System Partitioning Methodology
- Analyzing AI Engine Designs Using the Vitis Analyzer
- Versal AI Engine Application Debug and Event Trace
- Development Using the v++ Command Line Tools
- Custom Platform Development (Create a Custom Platform)
- Embedded Heterogeneous System Design Flow
Date / fecha:
March 6th and 7th 2025. 15.00 to 18:00 (CET – European Coordinated Time)
Jueves 6 y viernes 7 de marzo de 2025 de 15.00 a 18.00 (Horario coordinado europeo)
Pre-register:
