BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Electratraining//Eventos//ES
CALSCALE:GREGORIAN
METHOD:PUBLISH
BEGIN:VEVENT
UID:evento-19967-20261209@electratraining.org
DTSTAMP:20261028T014940Z
DTSTART;VALUE=DATE:20261209
DTEND;VALUE=DATE:20261212
SUMMARY:Diseño con FPGAs de AMD-Xilinx: VHDL Síntesis Lógica y Simulaci
 ón (2026)
DESCRIPTION:Más información e inscripción: https://electratraining.org/2
 026/vhdl-sintesis-simulacion-2/
URL:https://electratraining.org/2026/vhdl-sintesis-simulacion-2/
END:VEVENT
END:VCALENDAR