Escuela Politécnica Superior

El seminario es gratuito y ofrecido por Euroform y Enterpoint Ltd., UK (http://www.enterpoint.co.uk/) . Se dictará en la Escuela Politécnica Superior de la Universidad Autónoma de Madrid el día 14 de diciembre de 2006. El aforo se limita a 45 participantes. Al final de esta página puede obtener el formulario de inscripción on-line así como instrucciones de como llegar a la EPS-UAM.

El programa preliminar es el siguiente:

10:00 - 11:30: Functional Verification: An example view

11:30 - 12:00: Pausa Café

12:00 - 13:30: Cutting the Costs of Formal Verification with FPGA
Hardware Platforms

Descriptores:

Macro Verification Guidelines (Elías Todorovich , UAM). Seminario en castellano

- Motivation and Definitions

- Overview: Verification plan, Verification strategy

- Inspection, Adversarial testing

- Testbench design, Verification components

- Code coverage

- Verification Management Tools

Elías Todorovich es profesor de la Escuela Politecnica Superior de la UAM, trabajando desde hace 10 años con lógica programable, herramientas EDA y VHDL. Actualmente está investigando sobre el salto metodológico que se ha evidenciado en Verificacion Funcional y que está impactando fuertemente en la industria en este momento.

Functional Verification: An example view (Oswaldo Cadenas, University of Reading). Seminario en castellano

The most common and productive aspects for functional verification of the SystemVerilog language such as classes, constrained randomization, assertions, coverage, clocking blocks and program blocks are examined when applied to a simple but representative RTL design. Although simulation has been performed using Questa from Mentor, coding has followed well-documented language-oriented verification methodologies guidelines.

Dr. Cadenas lectures HDL, FPGA and computer architecture subjects at Reading (UK) with several publications in the compilation of algorithms into FPGAs. He is also a consultant to a spin-out company from Reading on FPGA prototyping.

Cutting the Costs of Formal Verification with FPGA Hardware Platforms (John Adair, Enterpoint Ltd.). Seminario en inglés

Focusing on the benefits of using a FPGA Hardware Platform, this
presentation shows how these platforms can be used to cut the duration and
cost of the Formal Verification of designs. The presentation examines the
mapping of ASIC designs into FPGAs with particular focus on the
implementation of multiple clock domains in modern FPGAs. The presentation also examines the use of FPGA imbedded logic analysers and how they can be used as supplemental inputs to the formal verification process.

John Adair has worked at the leading edge of engineering design for 20
years and in particular for the last 15 years in applying ASIC and FPGA technology to the military, telecom and commercial sectors. He is now CEO of Enterpoint Ltd., a worldwide supplier of ASIC and FPGA products including Development Boards, Intellectual Property, and other design and consultancy services.

Escuela Politécnica Superior 
Universidad Autónoma de Madrid
Ctra. Colmenar Km.15, 
28039 Madrid, España

Reserva de plaza

Como llegar a la EPS-UAM