Del 02-06-2021 al 03-06-2021
Diseño con FPGAs de Xilinx con Vivado: Temporización y Depuración – Incompany
Diseño con FPGAs de Xilinx con Vivado: Temporización y depuración
El objetivo de este training es dotar de los conocimientos necesarios para desarrollar sistemas basados dispositivos FPGAs eficientemente. Especial hincapié en los aspectos de temprización (timing) y la depuración en chip (debugging).
Temario de la formación:
1. FPGA Architecture
• Introduction to modern FPGA Architecture.
• Special emphasis in Aerospace devices Kintex KU40, KU60 FPGAs.
2. Vivado Tool
• Vivado Design Suite I/O Pin Planning layout to perform pin assignments in a design.
• Vivado IP Flow: Customize IP, instantiate IP, and verify the hierarchy of your design IP.
• Creating and Packaging Custom IP: Create your own IP and package and include it in the Vivado IP catalog.
• Using an IP Container: Use a core container file as a single file representation for an IP.
• Designing with the IP Integrator: Use the Vivado IP integrator to create a subsystem.
3. Timing Issues, Synchronous Design and Design Constrains
• Timing model and Static Timing Analysis (STA) in Xilinx FPGAs
• Introduction to Clock Constraints: Apply clock constraints and perform timing analysis.
• Generated Clocks: Use the report clock networks report to determine if there are any generated clocks in a design.
• I/O Constraints and Virtual Clocks: Apply I/O constraints and perform timing analysis.
• Timing Constraints Wizard
• Synchronous Design Techniques in an FPGA design.
• Vivado Timing Reports: Generate and use Vivado timing reports to analyze failed timing paths.
• Setup and Hold TimingAnalysis: Understand setup and hold timing analysis.
• Timing Constraints Editor: Introduces the specific editor tool to create timing constraints.
• Report Clock Networks: In order to view the primary and generated clocks in a design.
• Timing Summary Report: Use the post implementation timing summary report to signoff criteria for timing closure.
• Clock Group Constraints: Apply clock group constraints for asynchronous clock domains.
• Introduction to Timing Exceptions: Applying them to fine tune design timing.
4. Debugging: Simulation and Logic Analyzer, Power Estimation
• Use of external simulator. Examples with Mentor Model/QuestaSim
• Introduction to the Vivado Logic Analyzer: Overview of the Vivado
• Logic analyzer (former Chipscope) for debugging a design.
• Introduction to Triggering, Debug Cores
• Understand how the debug hub core is used to connect debug cores in a design.
• HDL Instantiation Debug Probing Flow
• Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
• Xilinx Power Estimator Spreadsheet: Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
• Power Analysis and Optimization Using the Vivado Design Suite
Formato de del curso:
El curso es teórico-práctico con una fuerte carga de ejercicios. Exclusivo para Thales Alenia Space.
Fechas:
Miércoles 2 y jueves 3 de junio de 2021 de 9 a 18h.
Lugar de realización:
Escuela Politécnica Superior
Universidad Autónoma de Madrid (UAM)
Francisco Tomás y Valiente, 11
28049 MADRID
Puede ver como llegar (Aquí).
