22-06-2022

Seminario Cadlog-Siemens EDA: Verifying Safety-Critical Applications

Verificación de aplicaciones de seguridad crítica (Safety Critical)

Verifying Safety-Critical Applications

Cadlog, distribuidor de Mentor-Siemens EDA (Anteriormente Mentor Graphics) nos ofrece este seminario titulado “Seminario Cadlog: Verifying Safety-Critical Applications”.  Puede ver los detalles en la página de Cadlog (aquí).

El seminario será presencial de 10.00 a 13.00 hs y se dicta en Inglés.

     

Introducción (English Below):

Los sistemas críticos para la seguridad son aquellos sistemas cuya falla podría provocar la pérdida de vidas, daños significativos a la propiedad o daños al medio ambiente.

Según los últimos estudios del grupo de investigación Wilson, más del 83% de los proyectos de diseño de FPGA todavía tienen errores no triviales que llegan al momento de la producción. Este número muestra el alcance del problema con los diseños de FPGA actuales.

Adicionalmente, la complejidad de los PCB está aumentando, lo que impulsa a los ingenieros a adoptar nuevas metodologías de diseño y verificación para abordar los desafíos relacionados con los estándares de seguridad.

El propósito de este seminario organizado por CADLOG, Siemens EDA y UAM es repasar las mejores prácticas desde la fase de captura de requisitos hasta la fase de producción.

Introduction

Safety-critical systems are those systems whose failure could result in loss of life, significant property damage, or damage to the environment.

According to the latest studies from Wilson research group, more than 83% of FPGA design projects still have non-trivial bugs which escape to production. This number shows the extent of the problem with today’s FPGA designs.

In addition the PCB complexity is increasing which drives engineers to adopt new design and verification methodologies to address challenges related to safety and compliance standards.

The purpose of this seminar organized by CADLOG, Siemens EDA and UAM is to overview best practices starting from the requirements capturing phase till the production phase.

Agenda (preliminar):

  • Introduction
  • Requirement Capture
  • State of the art Verification Technics
    • Simulation
    • Formal
    • Emulation
  • Requirement Traceability
  • System-Level PCB Analysis and Verification
  • Conclusion and Q&A

Fecha: 

Miércoles, 22 de junio de 2022. de 10.00 a 13.00.

Lugar:

Sala C-105, edificio C. – Escuela Politécnica Superior
Universidad Autónoma de Madrid (UAM)
Francisco Tomás y Valiente, 11
28049 MADRID

Puede ver como llegar (Aquí).

Speakears:

Rachid Laaris. A background in Microelectronics, Physics and more than 19 years of EDA experience. Rachid entered the Electronic Design Automation (EDA) in 1998 as an application engineer and continued his career to consultancy in signal integrity on behalf of European companies. As part of CADlog team, he is dedicated to deliver productive engineering and HDL development solutions to customers via the best in class software and support for tomorrows complex designs.

Rafik Bendahmane. Rafik Bendahmane has accumulated more than 10 years of experience in high-speed and circuit design and simulation at system and board level, he is certified CID Advanced which allow him to understand the industry challenges from design to manufacturing. Rafik Joined Mentor in 2017 as an applications engineer for Signal and Power Integrity solutions, he helps companies to deploy simulation methodologies and solutions to bring the digital twin to life. Rafik earned his M.Sc Microtechnologies for communication systems from the engineering school ESIEE-Paris.

Faïçal Chtourou. Faïçal Chtourou is a European application engineer at Siemens EDA, specialized in digital functional verification tools and methodology. His background includes 10+ years of experience verifying complex SOC in Various markets (HPC, Automotive, Flash memory ); he has a strong interest in flow automation and RTL quality improvement.

Faïçal holds an MS degree in Microelectronics and Telecommunication from Polytech Marseille, France.

Registro:

Registrarse en este evento a través de la página de CadLog (aquí).

 

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