Del 06-03-2023 al 08-03-2023

Diseño Avanzado con FPGAs de AMD-Xilinx: Temporización, depuración y optimización (incompany)

Diseño Avanzado con FPGAs de AMD-Xilinx: Temporización, depuración y optimización In-company Thales Alenia Space

El objetivo de este training es dotar de los conocimientos necesarios para desarrollar sistemas basados dispositivos FPGAs de AMD-Xilinx eficientemente. Especial hincapié en los aspectos de temporización (timing), la depuración en chip (debugging) y optimización de recursos.

Formato de del curso: El curso es teórico-práctico con una fuerte carga de ejercicios y formato presencial con una duración de 24 hs. docentes (3 días)

Temario de la formación: El contenido del curso será una adaptación de curso que se ofrece regular con el nombre VIV-ADV: Diseño con FPGAs de AMD-Xilinx: Vivado ML Edition – Advanced  con los siguientes descriptores:

1. FPGA Architecture
• Introduction to AMD-Xilinx FPGA, 3D IC, SSI, and SoC device architecture.
• UltraFast Design Methodology: Best practices in Vivado Design Flow.
• Special emphasis in Aerospace devices Kintex KU40, KU60 FPGAs.
2. Vivado ML Tool
• Vivado I/O Pin Planning layout to perform pin assignments in a design.
• Vivado IP Flow: Customize IP, instantiate IP, and verify the hierarchy of your design IP.
• Creating and Packaging Custom IP: Create your own IP and package and include it in the Vivado IP catalog.
• Using an IP Container: Use a core container file as a single file representation for an IP.
• Designing with the IP Integrator: Use the Vivado IP integrator to create a subsystem.
3. Debugging: Simulation and Logic Analyzer, Power Estimation
• Use of external simulator. Examples with Mentor Model/QuestaSim
• Introduction to the Vivado Logic Analyzer: Overview of the Vivado Logic analyzer (former Chipscope) for debugging a design.
• Introduction to Triggering, Debug Cores- Understand how the debug hub core is used to connect debug cores in a design.
• HDL Instantiation Debug Probing Flow
• Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
• Xilinx Power Estimator Spreadsheet: Estimate the number of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
• Power Analysis and Optimization Using the Vivado Design Suite
4. Timing Issues, Synchronous Design and Design Constrains
• Timing model and Static Timing Analysis (STA) in Xilinx FPGAs
• Introduction to Clock Constraints: Apply clock constraints and perform timing analysis.
• Generated Clocks: Use the report clock networks report to determine if there are any generated clocks in a design.
• I/O Constraints and Virtual Clocks: Apply I/O constraints and perform timing analysis.
• Vivado Timing Reports: Generate and use to analyze failed timing paths.
• Setup and Hold Timing Analysis: Understand setup and hold timing analysis.
• Timing Summary Report: Use the post implementation timing summary report to signoff criteria for timing closure.
• Clock Group Constraints: Apply clock group constraints for asynchronous clock domains.
• Introduction to Timing Exceptions: Applying them to fine tune design timing.
5. Advanced Vivado Tools, Design Techniques and TCL:
• Pipelining – In order to improve design performance.
• Inference – Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
• Hierarchical Design – Overview of the hierarchical design flows in Vivado.
• Introduction to Floorplanning – Introduction to floorplanning and how to use Pblocks.
• Design Analysis and Floorplanning – Explore the pre- and post-implementation design analysis features of the Vivado IDE.
• Congestion – Identifies congestion and addresses congestion issues.
• Incremental Compile Flow – How to use when making last-minute RTL changes.
• Physical Optimization – Use physical optimization techniques for timing closure.
• Introduction to Tcl Syntax and Structure. Intro to Design Analysis Using Tcl Commands
• Advanced TCL features. Introduction to the Xilinx Tcl Store. Procedures, list, and regexp (regular expressions) in Tcl Scripting.
• Debugging and Error Handling in Tcl Scripts. Manipulating Design Properties Using Tcl.

Fechas y Lugar:

  • 6 al 8 de marzo de 2023.

Escuela Politécnica Superior, Universidad Autónoma de Madrid (UAM)
Francisco Tomás y Valiente, 11. 28049 MADRID

Galería de imágenes