Diseño de Sistemas usando AMD Versal adaptive SoC (Incompany)

Diseño de Sistemas Avanzados en Dispositivos AMD (Xilinx) Versal ACAP para Thales AleniaSpace.

El curso es teórico-práctico, alternando contenidos teóricos y laboratorios.  Se desarrollo sobre tres bloques temáticos en 32 hs docentes:

Temario:

Module A. Architecture: Introduction; Architecture Overview; Design Tool Flow; Adaptable Engines (PL); SelectIO™ Resources; Clocking Architecture; Processing System; PMC and Boot and Configuration. System Interrupts; Timers, Counters, and RTC; DSP Engine; AI Engine. NoC Introduction and Concepts. Memory Solutions; Programming Interfaces; Serial Transceivers; System Migration.

Labs Module A:  Lab A01 Design Tool Flow; Lab A02 Clocking and IO Resources; Lab A03 Boot and Configuration; Lab A04 Creating a Square Root Application Using DSP Engines; Lab A05 Versal AI Engine Tool Flow; Lab A06 NoC Introduction and Concepts.

Module B. Design Methodology:  Embedded Software Development; Software Build Flow; Software Stack; Security Management and Safety Features; System and Solution Planning Methodology; Application Partitioning 1; Power Design Manager; Hardware, IP, and Platform Development Methodology; Timing Closure Overview and Techniques; System Integration and Validation Methodology; Configuration and Debugging; Overview of HSDP; Fabric Debug; System Simulation .

Labs Module B:  LabB01 Application Development and Debugging; Lab B02 Software Build Flow – PetaLinux Tools; Lab B03 Power Estimation for Versal Adaptive SoCs; Lab B04 Platform Creation. Lab B05 High-Speed Debug Port (HSDP). Lab B06 Programmable Logic Debugging. Lab B07 System Simulation

Module C. Advance topic (AIE, NoC, Mem): Versal AI Engine (AIE) Architecture and API. The Programming Model of AIE; Memory Interfaces (Memory Solutions Overview); DDRMC Hardened Memory Controller; Configuring and Simulating the DDRMC Hard Controller; Network on Chip (NoC), NoC DDR Memory Controller, NoC Performance Tuning; System Design Migration.

Fechas:

• Primera parte: 24 y 25 de septiembre 2024
• Segunda parte: 8 y 9 de octubre de 2024

Lugar de realización:

Escuela Politécnica Superior
Universidad Autónoma de Madrid (UAM)
Francisco Tomás y Valiente, 11
28049 MADRID