Dear course attendee,
This anonymous survey aims to know your previous knowledge and expectation of the course.
Please complete the survey in order to help us organize in the best way the training.
Position Not specified yetHardware EngineerSoftware EngineerSystem EngineerQuality EngineerProject Leaderother
Year of Experiency Not specified yet< 2 Years3-5 Years6-9 Years> 10 Years
Previous knowledge of VHDL (or Verilog) and RTL design
Experience in FPGA design? Which tools and devices?
Expectations of this training. Additionally, if you have a project in progress (or to start), please tell us the main requirements
Any comment that you consider relevant