28-03-2023
As part of the SPL2023 (XI Southern Programmable Logic Conference – https://www.splconf.org/spl23/) This workshop is part of this event.
Presentation:The evolution of reconfigurable computing in recent decades following Moore’s law was impressive. Xilinx (now AMD) was the inventor of the FPGA back in the early 80s, later introduce Adaptable SoC (system on a chip) and recently the ACAP (Adaptive Computing Acceleration Platform) architecture.
RTL code-based programming for FPGAs has evolved into new high-level paradigms that allow increasing the level of abstraction and addressing even more complex problems using Cloud Computing FPGA accelerators.
This wçorkshop will introduce the Vitis Unified Software Platform environment for developing FPGA accelerators. Vitis environment enables the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto heterogeneous CPU-FPGA-ACAP systems. Vitis supports: C and C++ kernels. RTL design flows are also supported for experienced hardware developers. Each of these flows will be discussed along with the open-source Xilinx Runtime Library and Vitis open-source accelerated libraries.
Lessons summary:
San Luis Argentina
SPL 2023 web page. https://www.splconf.org/spl23/