26-11-2024

Seminario Cadlog-Siemens EDA: Questa-Driven Verification Flow for High-Quality FPGA Designs

Seminario Questa-Driven Verification Flow for High-Quality FPGA Designs (CADLOG – Siemens EDA)

Cadlog, distribuidor de Mentor-Siemens EDA (Anteriormente Mentor Graphics) y profesores de la Universidad Politécnica de Valencia, nos ofrecen este seminario titulado “Questa-Driven Verification Flow for High-Quality FPGA Designs”.  Puede ver los detalles en la página de Cadlog (aquí).

El seminario será presencial de 9.00 a 16.30 hs. La sesión de la mañana se dicta en Inglés por la y en castellano la de por la tarde. Puede ver el flyer en pdf aquí.

     

Introducción (English Below):

Este seminario aborda los desafíos asociados a la verificación de diseños complejos de FPGA en el contexto de protocolos de alta velocidad y arquitecturas avanzadas de sistemas en chip. Ofrece un análisis exhaustivo de Siemens Questa verification suite, abarcando tanto métodos formales de simulación, con el fin de garantizar la calidad y la fiabilidad de los diseños de FPGA.

Como complemento se presenta una introducción avanzada a la simulación de sistemas complejos utilizando system verilog y UVM.

El propósito de este seminario organizado por CADLOG, Siemens EDA, profesores de la UPV y Electratraining es repasar las mejores prácticas en la verificación de diseños complejos en FPGA y Sistemsa en un Chip (SoC) configurables.

Introduction

This seminar addresses the challenges of verifying complex FPGA designs in the era of high-speed protocols and intricate system-on-chip architectures. It provides a deep dive into Siemens Questa verification suite, covering both simulation and formal methods to ensure high-quality, reliable FPGA designs.

As a complement, an advanced introduction to the simulation of complex systems using system verilog and UVM is presented.

The purpose of this seminar organized by CADLOG, Siemens EDA, UPV professors and Electratraining is to review best practices in the verification of complex designs in configurable FPGAs and Systems on a Chip (SoC).

Agenda (preliminar):

  • 9:00 – 9:30 – Welcome coffee
  • 9:30 – 10:00 – Introduction Cadlog Group & Siemens
  • 10:00 – 11:00 – Formal techniques for better design quality (in English)
    • Linting
    • Advanced linting
    • Code coverage closure
  • 13:00 – 14:00 – Lunch
  • 14:00 – 16:00 – Simulation (in Spanish)
    • Advanced test generation using System Verilog
    • Introduction to UVM
    • UVM testbench structure
  • 16:00 – 16:30 – Q&A – Conclusion

Fecha: 

Martes, 26 de noviembre de 2024. de 9.00 a 16.30.

Lugar:

Sala de grados edificio A – Escuela Politécnica Superior
Universidad Autónoma de Madrid (UAM)
Francisco Tomás y Valiente, 11
28049 MADRID

Puede ver como llegar (Aquí).

Speakears:

Rachid Laaris: key member of the Cadlog team bringing over twenty years of professional experience in Electronic Design Automation (EDA). He is a graduate in Microelectronics and Physics and began his career in the electronics industry as an Application Engineer in 1998, later specializing in signal integrity consulting for European organizations. His expertise includes delivering engineering solutions and HDL development for both current and future projects, utilizing high-quality software to address emerging design challenges.

Faïçal Chtourou: is an European Application Engineer at Siemens EDA, specialized in digital functional verification tools and methodology. His background includes over 10 years of experience verifying complex SoC in various markets (HPC, Automotive, Flash memory). He has a strong interest in flow automation and RTL quality improvement. Faïçal holds an MS degree in Microelectronics and Telecommunication from Polytech Marseille, France.

Gustavo D. Sutter: PhD in Computer Science and Telecommunications at the Universidad Autónoma de Madrid, and Systems Engineer at the Universidad Nacional del Centro de la Provincia de Buenos Aires. He has over 25 years of experience in FPGA-based system design. His expertise lies in computer architecture, digital design with FPGA, computer arithmetic and high-performance computing. He has collaborated on more than 50 research and technology transfer projects with companies. He is author of 3 books and over a hundred technical papers. He taught dozens of courses at various universities and is actively involved in corporate training. He is currently a professor and researcher at the Escuela Politécnica Superior de la Universidad Autónoma de Madrid and coordinates the tasks of the ElectraTraining initiative.

Rafael Gadea Gironés: Associate Professor at Universitat Politècnica de València. He has authored and coauthored around 45 refereed papers in journals and high-ranked conferences, has guided 5 doctoral theses, and has participated in more than 30 research projects. His research interest focuses on microelectronic design, implementation of artificial neural networks, design and verification of FPGA-based systems. Professor Gadea Gironés has a PhD in industrial engineering from Universitat Politècnica de València.

José María Monzo Ferrer: Associate Professor at the Universitat Politècnica de València, with a PhD in telecommunication engineering. He has contributed to over 30 refereed papers in journals and high-impact conferences, while actively participating in more than 16 research projects. His expertise lies in FPGA-based data acquisition systems for instrumentation, digital signal processing and microelectronic design. Professor Monzo Ferrer’s extensive academic work has made him a key figure in the fields of electronics and telecommunications, driving innovation through his research and publications.

Registro:

Registrarse en este evento a través de la página de CadLog (aquí).