On Line Seminar: Harnessing the Power of Versal AI Engines for DSP, AI, Image and real time applications

Seminario on line: Aprovechando el Poder de los Versal AI Engines para Aplicaciones de DSP, IA, Imagen y Tiempo Real

Presentación (In English below):

Este seminario introduce a ingenieros, investigadores y estudiantes avanzados a las capacidades de los AMD Versal Adaptive SoCs, con especial énfasis en la arquitectura AI Engine (AIE) y su papel en la aceleración de cargas de trabajo de procesamiento digital de señales (DSP), aprendizaje automático y procesamiento de datos en tiempo real de alto rendimiento.

Los participantes adquirirán experiencia en el desarrollo de aplicaciones para AI Engine, modelado de flujos de datos (dataflow) e integración con la lógica programable (PL) y los procesadores embebidos (PS) de la arquitectura Versal. El taller ofrece orientación práctica para diseñar pipelines, optimizar el rendimiento (throughput/latencia) y desplegar grafos de AI Engine utilizando las herramientas de Vitis.

Introduction (In English):

This seminar introduces engineers, researchers, and advanced students to the capabilities of AMD Versal Adaptive SoCs, with special emphasis on the AI Engine (AIE) architecture and its role in accelerating high-performance DSP, machine learning, and real-time data processing workloads.

Participants will gain experience with AI Engine application development, dataflow modeling, and integration with the programmable logic (PL) and embedded processors (PS) of the Versal architecture. The workshop provides practical guidance for designing pipelines, optimizing throughput/latency, and deploying AI Engine graphs using Vitis tools.

The seminar will be in Spanish.

Descriptores preliminares / Agenda (preliminary):

• Introduction to Versal Adaptive SoC.
  • Breakdown of PS, PL, AI Engine array, NoC
• AI Engine Architecture Deep Dive
  • AIE tile microarchitecture
  • Vector processing units and accumulation pipelines
  • Memory tiles, stream switches, cascade bus
  • Comparison with GPUs/DSPs/FPGAs
  • Programming models (AIE API, AIE Graph)
• Vitis Tool Flow for AIE Development
  • Project structure
  • Kernel development in C++
  • Graph creation and compilation
  • aiesimulator, x86simulator, hardware emulation
  • Analysis and debugging tools
• Programable Logic (PL)-AIE Interaction
  • AXI-Stream and PLIO
  • Designing custom PL accelerators with Vitis HLS
  • Synchronization and buffering between PL and AIE
• Application Examples
  • Real-time image processing pipeline (e.g., demosaic, filtering, enhancement)
  • Radar/communications channelization and beamforming
  • Neural network acceleration using AIE-ML

Fecha / Date:

Jueves 29 de enero de 2026 de 15:00 a 18:00h. (horario coordinado Europeo de verano)

Thursday, January 29th 2026 15:00 – 18:00 CEST.

Lugar de realización / Place:

Live on Line

Pre-registro / Pre-registration: